VHDL programming for gates
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This is 'VHDL programming for gates' assignment of Digital Design - Computer Engineering of Somaiya University - Gyaani Buddy
Implements a simple OR, AND, XOR, NOR, NAND, XNOR gate in VHDL
This is 'VHDL programming for gates' assignment of Digital Design - Computer Engineering of Somaiya University - Gyaani Buddy
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VHDL is an acronym for VHSlC Hardware Description Language (VHSIC is an acronym for Very High Speed Integrated Circuits). It is a hardware description language that can be used to model a digital system at many levels of abstraction ranging from the algorithmic level to the gate level. The complexity of the digital system being modeled could vary from that of a simple gate to a complete digital electronic system, or anything in between. The digital system can also be described hierarchically. Timing can also be explicitly modeled in the same description.
VHDL Programming Structure
Entity and Architecture are the two main basic programming structures in VHDL.
Entity: Entity can be seen as the black box view of the system. We define the inputs and outputs of the system which we need to interface. It is used to declare the I/O ports of the circuit.
Eg:
Entity ANDGATE is
Port (A: in std_logic;
B: in std_logic;
Y: out std_logic);
End entity ANDGATE;
Entity name ANDGATE is given by the programmer, each entity must have a name.
Architecture: Architecture defines what is in our black box that we described using ENTITY. The description code resides within architecture portion. Either behavioral or structural models can be used to describe our system in the architecture. In Architecture we will have interconnections, processes, components, etc.
Eg:
Architecture AND1 of ANDGATE is
--declarations
Begin
--statements
Y <= A AND B;
End architecture AND1;
Entity name or architecture name is user defined. Identifiers can have uppercase alphabets, lowercase alphabets, and numbers and underscore (_). First letter of identifier must be an alphabet and identifier cannot end with an underscore. In VHDL, keywords and user identifiers are case insensitive.
VHDL is strongly typed language i.e. every object must be declared. Standardized design libraries are typically used and are included prior to the entity declaration. This is accomplished by including the code "library ieee;" and "use ieee.std_logic_1164.all;"
Implementation Details:
VHDL program code
OR
Code:
library ieee;
use ieee.std_logic_1164.all;
entity OR_ent is
port ( x : in std_logic;
y: in std_logic;
f: out std_logic);
end OR_ent;
architecture OR_arch of OR_ent is
begin
process(x,y)
begin
if((x='0') and (y='0')) then
f<= '0';
else
f<='1';
end if;
end process;
end OR_arch;
Wave Form:
AND
Code:
library ieee;
use ieee.std_logic_1164.all;
entity AND_ent is
port ( x : in std_logic;
y : in std_logic;
f : out std_logic);
end AND_ent;
architecture AND_arch of AND_ent is
begin
process(x,y)
begin
if((x='1') and (y='1')) then
f<='1';
else
f<='0';
end if;
end process;
end AND_arch;
Wave Form:
XOR
Code:
library ieee;
use ieee.std_logic_1164.all;
entity EXOR_ent is
port ( x : in std_logic;
y : in std_logic;
f : out std_logic);
end EXOR_ent;
architecture EXOR_arch of EXOR_ent is
begin
process(x,y)
begin
if((x=y)) then
f<='0';
else
f<='1';
end if;
end process;
end EXOR_arch;
Wave Form:
NOT
Code:
library ieee;
use ieee.std_logic_1164.all;
entity NOT_ent is
port ( x : in std_logic;
f : out std_logic);
end NOT_ent;
architecture NOT_arch of NOT_ent is
begin
process(x)
begin
if (x='1') then
f<='0';
else
f<='1';
end if;
end process;
end NOT_arch;
Wave Form:
NOR
Code:
library ieee;
use ieee.std_logic_1164.all;
entity NOR1_ent is
port ( x : in std_logic;
y : in std_logic;
f : out std_logic);
end NOR1_ent;
architecture NOR1_arch of NOR1_ent is
begin
process(x,y)
begin
if((x='0') and (y='0')) then
f<='1';
else
f<='0';
end if;
end process;
end NOR1_arch;
Wave Form:
NAND
Code:
library ieee;
use ieee.std_logic_1164.all;
entity NAND_ent is
port ( x : in std_logic;
y : in std_logic;
f : out std_logic);
end NAND_ent;
architecture NAND_arch of NAND_ent is
begin
process(x,y)
begin
if((x='1') and (y='1')) then
f<='0';
else
f<='1';
end if;
end process;
end NAND_arch;
Wave Form:
XNOR
Code:
library ieee;
use ieee.std_logic_1164.all;
entity EXNOR_ent is
port ( x : in std_logic;
y : in std_logic;
f : out std_logic);
end EXNOR_ent;
architecture EXNOR_arch of EXNOR_ent is
begin
process(x,y)
begin
if((x=y)) then
f<='1';
else
f<='0';
end if;
end process;
Wave Form:
Q. What are two types of HDL?
Ans.
In computer engineering, a hardware description language (HDL) is a specialized computer language used to describe the structure and behavior of electronic circuits, and most commonly, digital logic circuits.
The two types of HDL are:
1. Verilog:
Verilog, standardized as IEEE 1364, is a hardware description language (HDL) used to model electronic systems. It is most commonly used in the design and verification of digital circuits at the register-transfer level of abstraction. It is also used in the verification of analog circuits and mixed-signal circuits, as well as in the design of genetic circuits.
2. VHDL:
VHDL stands for (VHSIC Hardware Description Language) is a hardware description language used in electronic design VHDL can also be used as a general purpose parallel programming language. VHDL is case sensitive language.